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  1. product pro?le 1.1 general description logic level n-channel enhancement mode field-effect transistor (fet) in a plastic package using trenchmos technology. 1.2 features 1.3 applications 1.4 quick reference data 2. pinning information PH5525L n-channel trenchmos logic level fet rev. 02 5 december 2006 product data sheet n logic level threshold n lead-free package n optimized for use in dc-to-dc converters n very low switching and conduction losses n 100 % r g tested n dc-to-dc converters n switched-mode power supplies n voltage regulators n pc motherboards n v ds 25 v n i d 81.7 a n r dson 5.5 m w n q gd = 3.3 nc (typ) table 1. pinning pin description simpli?ed outline symbol 1, 2, 3 source (s) sot669 (lfpak) 4 gate (g) mb mounting base; connected to drain (d) mb 1234 s d g mbb076
PH5525L_2 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 02 5 december 2006 2 of 12 nxp semiconductors PH5525L n-channel trenchmos logic level fet 3. ordering information 4. limiting values table 2. ordering information type number package name description version PH5525L lfpak plastic single-ended surface-mounted package; 4 leads sot669 table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ds drain-source voltage 25 c t j 150 c - 25 v v dgr drain-gate voltage (dc) 25 c t j 150 c; r gs =20k w -25v v gs gate-source voltage - 20 v i d drain current t mb =25 c; v gs = 10 v; see figure 2 and 3 - 81.7 a t mb = 100 c; v gs = 10 v; see figure 2 - 51.7 a i dm peak drain current t mb =25 c; pulsed; t p 10 m s; see figure 3 - 300 a p tot total power dissipation t mb =25 c; see figure 1 - 62.5 w t stg storage temperature - 55 +150 c t j junction temperature - 55 +150 c source-drain diode i s source current t mb =25 c - 52 a i sm peak source current t mb =25 c; pulsed; t p 10 m s - 208 a avalanche ruggedness e ds(al)s non-repetitive drain-source avalanche energy unclamped inductive load; i d = 45 a; t p = 0.1 ms; v ds 25 v; r gs =50 w ; v gs = 10 v; starting at t j =25 c - 100 mj
PH5525L_2 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 02 5 december 2006 3 of 12 nxp semiconductors PH5525L n-channel trenchmos logic level fet fig 1. normalized total power dissipation as a function of mounting base temperature fig 2. normalized continuous drain current as a function of mounting base temperature t mb =25 c; i dm is single pulse fig 3. safe operating area; continuous and peak drain currents as a function of drain-source voltage 03aa15 0 40 80 120 0 50 100 150 200 t mb p der (%) ( c) 03aa23 0 40 80 120 0 50 100 150 200 (%) i der t mb ( c) p der p tot p tot 25 c () ----------------------- - 100 % = i der i d i d25 c () -------------------- 100 % = 003aab437 1 10 10 2 10 3 10 -1 1 10 10 2 v ds (v) i d (a) dc 1 ms 100 m s limit r dson = v ds / i d 10 ms 100 ms 10 m s t p =
PH5525L_2 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 02 5 december 2006 4 of 12 nxp semiconductors PH5525L n-channel trenchmos logic level fet 5. thermal characteristics table 4. thermal characteristics symbol parameter conditions min typ max unit r th(j-mb) thermal resistance from junction to mounting base see figure 4 --2k/w fig 4. transient thermal impedance from junction to mounting base as a function of pulse duration 003aab438 10 -2 10 -1 1 10 10 -5 10 -4 10 -3 10 -2 10 -1 1 10 t p (s) z th(j-mb) (k/w) single pulse 0.2 0.1 0.05 d = 0.5 0.02 t p t p t t p t d =
PH5525L_2 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 02 5 december 2006 5 of 12 nxp semiconductors PH5525L n-channel trenchmos logic level fet 6. characteristics table 5. characteristics t j =25 c unless otherwise speci?ed. symbol parameter conditions min typ max unit static characteristics v (br)dss drain-source breakdown voltage i d = 250 m a; v gs =0v t j =25 c 25--v t j = - 55 c 22.5 - - v v gs(th) gate-source threshold voltage i d = 1 ma; v ds =v gs ; see figure 9 and 10 t j =25 c 1.3 1.7 2.15 v t j = 150 c 0.8 - - v t j = - 55 c - - 2.6 v i dss drain leakage current v ds =25v; v gs =0v t j =25 c --1 m a t j = 150 c - - 100 m a i gss gate leakage current v gs = 16 v; v ds = 0 v - - 100 na r g gate resistance f = 1 mhz - 1.8 - w r dson drain-source on-state resistance v gs = 10 v; i d = 25 a; see figure 6 and 8 t j =25 c - 4 5.5 m w t j = 150 c - 6.8 9.35 m w v gs = 4.5 v; i d = 25 a; see figure 6 and 8 - 5.9 8.2 m w dynamic characteristics q g(tot) total gate charge i d = 25 a; v ds =12v; v gs = 4.5 v; see figure 11 and 12 - 16.6 - nc q gs gate-source charge - 8 - nc q gs1 pre-v gs(th) gate-source charge - 3.4 - nc q gs2 post-v gs(th) gate-source charge - 4.6 - nc q gd gate-drain charge - 3.3 - nc v gs(pl) gate-source plateau voltage - 3.1 - v c iss input capacitance v gs =0v; v ds = 12 v; f = 1 mhz; see figure 14 -2150-pf c oss output capacitance - 500 - pf c rss reverse transfer capacitance - 225 - pf c iss input capacitance v gs =0v; v ds = 0 v; f = 1 mhz - 2460 - pf t d(on) turn-on delay time v ds =12v; r l = 0.5 w ; v gs = 4.5 v; r g = 5.6 w -25-ns t r rise time -55-ns t d(off) turn-off delay time - 28 - ns t f fall time -17-ns source-drain diode v sd source-drain voltage i s = 25 a; v gs = 0 v; see figure 13 - 0.83 1.2 v t rr reverse recovery time i s = 20 a; di s /dt = - 100 a/ m s; v gs = 0 v - 33.2 - ns q r recovered charge - 10.8 - nc
PH5525L_2 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 02 5 december 2006 6 of 12 nxp semiconductors PH5525L n-channel trenchmos logic level fet t j =25 ct j =25 c fig 5. output characteristics: drain current as a function of drain-source voltage; typical values fig 6. drain-source on-state resistance as a function of drain current; typical values t j =25 c and 150 c; v ds >i d r dson fig 7. transfer characteristics: drain current as a function of gate-source voltage; typical values fig 8. normalized drain-source on-state resistance factor as a function of junction temperature 003aab439 0 20 40 60 80 100 0 0.2 0.4 0.6 0.8 1 v ds (v) i d (a) 3.8 3.6 4 3 5 3.4 10 4.5 v gs (v) = 2.8 3.2 003aab440 0 4 8 12 16 20 0 20406080100 i d (a) r dson (m w ) 4 3.6 3.4 3.8 4.5 5 10 v gs (v) = 3.2 003aab441 0 20 40 60 80 012345 v gs (v) i d (a) t j = 150 c 25 c 003aab467 0 0.4 0.8 1.2 1.6 2 -60 0 60 120 180 t j ( c) a a r dson r dson 25 c () ----------------------------- - =
PH5525L_2 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 02 5 december 2006 7 of 12 nxp semiconductors PH5525L n-channel trenchmos logic level fet i d = 1 ma; v ds =v gs t j =25 c; v ds =5v fig 9. gate-source threshold voltage as a function of junction temperature fig 10. sub-threshold drain current as a function of gate-source voltage i d = 25 a; v ds = 12 v and 19 v fig 11. gate-source voltage as a function of gate charge; typical values fig 12. gate charge waveform de?nitions 003aab272 0 0.5 1 1.5 2 2.5 3 -60 0 60 120 180 t j ( c) v gs(th) (v) max typ min 003aab271 10 -6 10 -5 10 -4 10 -3 00.511.522.5 v gs (v) i d (a) max typ min 003aab442 0 2 4 6 8 10 0 10203040 q g (nc) v gs (v) i d = 25 a t j = 25 c v ds = 19 v 12 v 003aaa508 v gs v gs(th) q gs1 q gs2 q gd v ds q g(tot) i d q gs v gs(pl)
PH5525L_2 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 02 5 december 2006 8 of 12 nxp semiconductors PH5525L n-channel trenchmos logic level fet t j =25 c and 150 c; v gs =0v v gs = 0 v; f = 1 mhz fig 13. source current as a function of source-drain voltage; typical values fig 14. input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aab443 0 20 40 60 80 0.2 0.4 0.6 0.8 1 v sd (v) i s (a) t j = 25 c 150 c 003aab444 10 2 10 3 10 4 10 -1 1 10 10 2 v ds (v) c (pf) c iss c rss c oss
PH5525L_2 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 02 5 december 2006 9 of 12 nxp semiconductors PH5525L n-channel trenchmos logic level fet 7. package outline fig 15. package outline sot669 (lfpak) references outline version european projection issue date iec jedec jeita sot669 mo-235 04-10-13 06-03-16 0 2.5 5 mm scale e e 1 b c 2 a 2 a 2 bc a e unit dimensions (mm are the original dimensions) mm 1.10 0.95 a 3 a 1 0.15 0.00 1.20 1.01 0.50 0.35 b 2 4.41 3.62 b 3 2.2 2.0 b 4 0.9 0.7 0.25 0.19 c 2 0.30 0.24 4.10 3.80 6.2 5.8 h 1.3 0.8 l 2 0.85 0.40 l 1.3 0.8 l 1 8 0 wy d (1) 5.0 4.8 e (1) 3.3 3.1 e 1 (1) d 1 (1) max 0.25 4.20 1.27 0.25 0.1 1 234 mounting base d 1 c plastic single-ended surface-mounted package (lfpak); 4 leads sot669 e b 2 b 3 b 4 h d l 2 l 1 a a w m c c x 1/2 e yc q q (a ) 3 l a a 1 detail x note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included.
PH5525L_2 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 02 5 december 2006 10 of 12 nxp semiconductors PH5525L n-channel trenchmos logic level fet 8. revision history table 6. revision history document id release date data sheet status change notice supersedes PH5525L_2 20061205 product data sheet - PH5525L_1 modi?cations: ? section 1.2 : updated the list PH5525L_1 20061010 product data sheet - -
PH5525L_2 ? nxp b.v. 2006. all rights reserved. product data sheet rev. 02 5 december 2006 11 of 12 nxp semiconductors PH5525L n-channel trenchmos logic level fet 9. legal information 9.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 9.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 9.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 9.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. trenchmos is a trademark of nxp b.v. 10. contact information for additional information, please visit: http://www .nxp.com for sales of?ce addresses, send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors PH5525L n-channel trenchmos logic level fet ? nxp b.v. 2006. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 5 december 2006 document identifier: PH5525L_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 11. contents 1 product pro?le . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 general description. . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 quick reference data. . . . . . . . . . . . . . . . . . . . . 1 2 pinning information . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 thermal characteristics. . . . . . . . . . . . . . . . . . . 4 6 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 9 legal information. . . . . . . . . . . . . . . . . . . . . . . 11 9.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 9.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10 contact information. . . . . . . . . . . . . . . . . . . . . 11 11 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12


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